1. Field of the Invention
This invention relates generally to methods for testing semiconductor circuitry for operability. More particularly, the invention pertains to interconnects and methods for fabrication thereof which are suitable for testing circuits of a bare die or multiple dice of an unsingulated wafer substantially without or with minimal "cross-talk" or other electrical interference.
2. State of the Art
In the current state of the art, bare semiconductor dice are finding increased use in constructions of multi-chip-modules having a large number of dice. Multi-chip, modules are particularly vulnerable to semiconductor die defects, because if only one of the multiple, e.g. 10-30 or more dice is defective, the module is considered defective and is generally discarded at considerable monetary loss. Thus, for example, if the individual die has a mean acceptance rate of 98.0 percent, a series of multi-chip-modules, each with 25 dice, would have a predicted overall acceptance rate of about 70 percent, which is unacceptable from the standpoint of production cost and resulting price to the customer. A multi-chip-module having a greater number of dice will have a lower acceptance rate.
In view of requirements for greater reliability of increasingly complex integrated circuits such as are included in multi-chip-modules (MCM), semiconductor manufacturers now supply bare, i.e. unencapsulated dice which have been pre-tested for operability in accordance with a set of specifications. Dice meeting the manufacturer's test specifications are certified as known-good-die (KGD).
Considerable effort has been expended to develop test equipment and methods for accurately testing an individual or discrete semiconductor die to enable KGD certification. For example, apparatus for conducting burn-in tests for a discrete die are disclosed in U.S. Pat. No. 4,899,107 to Corbett et al. and U.S. Pat. No. 5,302,891 to Wood et al., both patents assigned to Micron Technology, Inc. Other test apparatus for a discrete die are disclosed in U.S. Pat. No. 5,123,850 to Elder et al., and U.S. Pat. No. 5,073,117 to Malhi et al., both assigned to Texas Instruments, and in U.S. Pat. Nos. 5,451,165 of Cearley-Cabbiness et al., 5,475,317 of Smith, 5,572,140 of Lim et al., 5,406,210 of Pedder, 5,378,981 of Higgins III, 5,402,077 of Agahdel et al., and 5,565,767 of Yoshimizu et al.
In order to test a discrete semiconductor die, temporary electrical connections must be made between the bond pads on a bare semiconductor die and the external test circuitry of the test apparatus using the bond pads of the die to provide the connection points for testing the integrated circuit of the die. Bond pads on semiconductor dice are typically formed of layers of various metals, such as aluminum, copper, nickel, gold, alloys thereof, or solder of various metallurgies. The bond pads of semiconductor die for connections thereto are typically formed in a flat planar configuration or as a raised bump.
The test apparatus for discrete semiconductor die use various techniques for making a non-permanent connection to the bond pads of a semiconductor die. The Wood et al. patent shows a die contact member that uses non-bonded TAB (tape automated bonding) technology. The Elder et al. apparatus uses a flexible connection member having an arrangement of probe bumps or members for temporary contact with the wire bond pads of the semiconductor die. The Malhi et al. apparatus uses an arrangement of cantilevered probe tips to contact the bond pads of the semiconductor die.
In U.S. Pat. No. 5,326,428 of Farnworth et al., a method for fabricating a probe is disclosed which is used for non-permanent test contact with a bond pad on a semiconductor die.
U.S. Pat. No. 5,517,752 of Sakata et al. discloses a probe provided on a pressure-connector terminal used for TAB and COG connection to the bond pads of the semiconductor die.
One disadvantage of prior art test fixtures for semiconductor die testing, such as probe cards, is that their use often results in electronic interference; i.e., "cross-talk" between fixture leads, even at what are considered to be moderate frequencies for testing the die. This problem essentially precludes the application of existing test fixtures such as probe cards to the simultaneous testing of multiple bare semiconductor dice. Another problem in testing multiple semiconductor dice in wafer form is that of misalignment and disconnection of contact members from bond pads of dice being tested resulting from a probe card and the wafer containing the dice each having different coefficients of thermal expansion. Thus, each discrete semiconductor die of a wafer or multi-chip-module (MCM) must be separately tested, one at a time, resulting in much greater testing time and expense than are desirable. The need for apparatus and methods enabling rapid testing of multiple bare semiconductor dice is evident.